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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product wsf512k16-xxx 512k x 16 sram/flash module, smd 5962-96901 features n access times of 35ns (sram) and 90ns (flash) n access times of 70ns (sram) and 120ns (flash) n packaging ? 66 pin, pga type, 1.385" square hip, hermetic ceramic hip (package 402) ? 68 lead, hermetic cqfp (g2), 22mm (0.880") square (package 500). designed to fit jedec 68 lead 0.990 cqfj footprint (fig. 2) n 512kx16 sram n 512kx16 5v flash n organized as 512kx16 of sram and 512kx16 of flash memory with separate data busses n both blocks of memory are user configurable as 1mx8 n low power cmos n commercial, industrial and military temperature ranges n ttl compatible inputs and outputs n built-in decoupling caps and multiple ground pins for low noise operation n weight - 13 grams typical fig. 1 pin configuration for wsf512k16-xh2x fwe fcs fwe fcs swe scs 512k x 8 sram 8 sd 0-7 1 1 512k x 8 sram 8 sd 8-15 2 2 512k x 8 flash 8 fd 0-7 1 1 512k x 8 flash 8 fd 8-15 2 2 a 0 - 18 oe swe scs pin description fd 0-15 flash data inputs/outputs sd 0-15 sram data inputs/outputs a 0-18 address inputs swe 1-2 sram write enable scs 1-2 sram chip selects oe output enable v cc power supply gnd ground nc not connected fwe 1-2 flash write enable fcs 1-2 flash chip select sd 8 sd 9 sd 10 a 13 a 14 a 15 a 16 a 18 sd 0 sd 1 sd 2 swe 2 scs 2 gnd sd 11 a 10 a 11 a 12 v cc scs 1 nc sd 3 sd 15 sd 14 sd 13 sd 12 oe a 17 swe 1 sd 7 sd 6 sd 5 sd 4 fd 8 fd 9 fd 10 a 6 a 7 nc a 8 a 9 fd 0 fd 1 fd 2 v cc fcs 2 fwe 2 fd 11 a 3 a 4 a 5 fwe 1 fcs 1 gnd fd 3 fd 15 fd 14 fd 13 fd 12 a 0 a 1 a 2 fd 7 fd 6 fd 5 fd 4 11 22 33 44 55 66 1 12 23 34 45 56 top view flash memory features n 100,000 erase/program cycles n sector architecture ? 8 equal size sectors of 64k bytes each ? any combination of sectors can be concurrently erased. also supports full chip erase n 5 volt programming; 5v 10% supply n embedded erase and program algorithms n hardware write protection n page program operation and internal program control time. note: programming information available upon request. october 2000 rev. 5 block diagram
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com top view fig. 2 pin configuration for WSF512K16-XG2X 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 sd 0 sd 1 sd 2 sd 3 sd 4 sd 5 sd 6 sd 7 gnd sd 8 sd 9 sd 10 sd 11 sd 12 sd 13 sd 14 sd 15 v cc a 11 a 12 a 13 a 14 a 15 a 16 scs 1 oe scs 2 a 17 swe 2 fwe 1 fwe 2 a 18 nc nc fd 0 fd 1 fd 2 fd 3 fd 4 fd 5 fd 6 fd 7 gnd fd 8 fd 9 fd 10 fd 11 fd 12 fd 13 fd 14 fd 15 nc a 0 a 1 a 2 a 3 a 4 a 5 fcs 1 gnd fcs 2 swe 1 a 6 a 7 a 8 a 9 a 10 v cc fwe fcs fwe fcs swe scs 512k x 8 sram 8 sd 0-7 1 1 512k x 8 sram 8 sd 8-15 2 2 512k x 8 flash 8 fd 0-7 1 1 512k x 8 flash 8 fd 8-15 2 2 a 0 - 18 oe swe scs block diagram pin description fd 0-15 flash data inputs/outputs sd 0-15 sram data inputs/outputs a 0-18 address inputs swe 1-2 sram write enable scs 1-2 sram chip selects oe output enable v cc power supply gnd ground nc not connected fwe 1-2 flash write enable fcs 1-2 flash chip select the wedc 68 lead g2 cqfp fills the same fit and function as the jedec 68 lead cqfj or 68 plcc. but the g2 has the tce and lead inspection advantage of the cqfp form. wsf512k16-xxx 0.940"
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com wsf512k16-xxx absolute maximum ratings dc characteristics (v cc = 5.0v, v ss = 0v, t a = -55 c to +125 c) parameter symbol conditions min max unit input leakage current i li v cc = 5.5, v in = gnd to v cc 10 m a output leakage current i lo fcs = scs = v ih , oe = v ih, v out = gnd to v cc 10 m a sram operating supply current x 16 mode i ccx16 scs = v il , oe = v ih, f = 5mhz, v cc = 5.5, fcs = v ih 330 ma standby current i sb fcs = scs = v ih , oe = v ih, f = 5mhz, v cc = 5.5 45 ma sram output low voltage v ol i ol = 8ma, v cc = 4.5, fcs = v ih 0.4 v sram output high voltage v oh i ol = -4.0ma, v cc = 4.5, fcs = v ih 2.4 v flash v cc active current for read (1) i cc1 fcs = v il , oe = v ih , scs = v ih 130 ma flash v cc active current for program or i cc2 fcs = v il , oe = v ih , scs = v ih 150 ma erase (2) flash output low voltage v ol i ol = 8.0ma, v cc = 4.5, scs = v ih 0.45 v flash output high voltage v oh1 i oh = -2.5 ma, v cc = 4.5, scs = v ih 0.85 x v cc v flash low v cc lock out voltage v lko 3.2 4.2 v parameter flash data retention 20 years flash endurance (write/erase cycles) 100,000 notes: 1. stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. parameter symbol min max unit supply voltage v cc 4.5 5.5 v input high voltage v ih 2.2 v cc + 0.3 v input low voltage v il -0.5 +0.8 v recommended operating conditions parameter symbol min max unit operating temperature t a -55 +125 c storage temperature t stg -65 +150 c signal voltage relative to gnd v g -0.5 7.0 v junction temperature t j 150 c supply voltage v cc -0.5 7.0 v sram truth table scs oe swe mode data i/o power h x x standby high z standby l l h read data out active l h h read high z active l x l write data in active capacitance (t a = +25 c) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (@ 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded algorithm (program or erase) is in progress. 3. dc test conditions: v il = 0.3v, v ih = v cc - 0.3v test symbol condition max unit oe capacitance c oe v in = 0v, f = 1.0mhz 50 pf f/s we 1-2 capacitance c we v in = 0v, f = 1.0mhz 20 pf f/s cs 1-2 capacitance c cs v in = 0v, f = 1.0mhz 20 pf data i/o capacitance c i/o v in = 0v, f = 1.0mhz 20 pf address input capacitance c ad v in = 0v, f = 1.0mhz 50 pf this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com parameter symbol -35 -70 unit read cycle min max min max read cycle time t rc 35 70 ns address access time t aa 35 70 ns output hold from address change t oh 05ns chip select access time t acs 35 70 ns output enable to output valid t oe 25 35 ns chip select to output in low z t clz 1 410ns output enable to output in low z t olz 1 05ns chip disable to output in high z t chz 1 15 25 ns output disable to output in high z t ohz 1 15 25 ns 1. this parameter is guaranteed by design but not tested. sram ac characteristics (v cc = 5.0v, t a = -55 c to +125 c) parameter symbol -35 -70 unit write cycle min max min max write cycle time t wc 35 70 ns chip select to end of write t cw 25 60 ns address valid to end of write t aw 25 60 ns data valid to end of write t dw 20 30 ns write pulse width t wp 25 50 ns address setup time t as 00ns address hold time t ah 05ns output active from end of write t ow 1 05ns write enable to output in high z t whz 1 15 25 ns data hold from write time t dh 00ns 1. this parameter is guaranteed by design but not tested. sram ac characteristics (v cc = 5.0v, t a = -55 c to +125 c) notes: v z is programmable from -2v to +7v. i ol & i oh programmable from 0 to 16ma. tester impedance z 0 = 75 w . v z is typically the midpoint of v oh and v ol . i ol & i oh are adjusted to simulate a typical resistive load circuit. ate tester includes jig capacitance. fig. 3 ac test circuit ac test conditions parameter typ unit input pulse levels v il = 0, v ih = 3.0 v input rise and fall 5 ns input and output reference level 1.5 v output timing reference level 1.5 v i current source d.u.t. c = 50 pf eff i ol v 1.5v (bipolar supply) z current source oh wsf512k16-xxx
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 4 sram timing waveform - read cycle fig. 5 sram write cycle - swe controlled address data i/o write cycle 1, swe controlled t aw t cw t ah t wp t dw t whz t as t ow t dh t wc data valid scs swe ws32k32-xhx fig. 6 sram write cycle - scs controlled address data i/o write cycle 2, scs controlled t aw t as t cw t ah t wp t dh t dw t wc scs swe data valid address data i/o read cycle 2, (swe = v ih ) t aa t acs t oe t clz t olz t ohz t rc data valid high impedance scs soe t chz address data i/o read cycle 1, (scs = oe = v il , swe = v ih ) t aa t oh t rc data valid previous data valid wsf512k16-xxx
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com flash ac characteristics C write/erase/program operations, fwe controlled (v cc = 5.0v, t a = -55 c to +125 c) parameter symbol -90 -120 unit min max min max write cycle time t avav t wc 90 120 ns chip select setup time t elwl t cs 00ns write enable pulse width t wlwh t wp 45 50 ns address setup time t avwl t as 00ns data setup time t dvwh t ds 45 50 ns data hold time t whdx t dh 00ns address hold time t wlax t ah 45 50 ns write enable pulse width high t whwl t wph 20 20 ns duration of byte programming operation (1) t whwh1 300 300 m s sector erase time (2) t whwh2 15 15 sec read recovery time before write t ghwl 00 m s v cc set-up time t vcs 50 50 m s chip programming time 11 11 sec chip select hold time t oeh 10 10 ns chip erase time (3) 64 64 sec flash ac characteristics C read only operations (v cc = 5.0v, t a = -55 c to +125 c) parameter symbol -90 -120 unit min max read cycle time t avav t rc 90 120 ns address access time t avqv t acc 90 120 ns chip select access time t elqv t ce 90 120 ns oe to output valid t glqv t oe 35 50 ns chip select to output high z (1) t ehqz t df 20 30 ns oe high to output high z (1) t ghqz t df 20 30 ns output hold from address, cs or oe change, whichever is first t axqx t oh 00 ns 1. guaranteed by design, not tested. 1. typical value for t whwh1 is 7ns. 2. typical value for t whwh2 is 1sec. 3. typical value for chip erase time is 8sec. wsf512k16-xxx
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com parameter symbol -90 -120 unit min max write cycle time t avav t wc 90 120 ns fwe setup time t wlel t ws 00ns fcs pulse width t eleh t cp 45 50 ns address setup time t avel t as 00ns data setup time t dveh t ds 45 50 ns data hold time t ehdx t dh 00ns address hold time t elax t ah 45 50 ns fcs pulse width high t ehel t cph 20 20 ns duration of programming operation (1) t whwh1 300 300 m s sector erase time (2) t whwh2 15 15 sec read recovery time t ghel 00ns chip programming time 11 11 sec chip erase time (3) 64 64 sec 1. typical value for t whwh1 is 7ns. 2. typical value for t whwh2 is 1sec. 3. typical value for chip erase time is 8sec. flash ac characteristics C write/erase/program operations, fcs controlled (v cc = 5.0v, t a = -55 c to +125 c) wsf512k16-xxx
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 7 ac waveforms for flash memory read operations addresses fcs oe fwe outputs high z addresses stable t oe t rc output valid t ce t acc t oh high z t df wsf512k16-xxx
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 8 write/erase/program operation, flash memory fwe controlled notes : 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. addresses fcs oe fwe data 5.0 v 5555h pa pa t wc t cs pd d 7 d out t ah t wph t dh t ds data polling t as t rc t wp a0h t oe t df t oh t ce t ghwl t whwh1 wsf512k16-xxx
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 9 ac waveforms chip/sector erase operations for flash memory notes: 1. sa is the sector address for sector erase. addresses fcs oe fwe data v cc 5555h 2aaah 2aaah sa 5555h 5555h t wp t cs t vcs 10h/30h 55h 80h 55h aah aah t ah t as t ghwl t wph t dh t ds wsf512k16-xxx
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 10 ac waveforms for data polling during embedded algorithm operations for flash memory fcs oe fwe t oe t oe t ce t ch t oh d7 d7 = valid data high z d0-d6 = invalid d0-d7 valid data t df d7 d0-d6 t oeh t whwh 1 or 2 wsf512k16-xxx
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com fig. 11 write/erase/program operation for flash memory, cs controlled notes: 1. pa represents the address of the memory location to be programmed. 2. pd represents the data to be programmed at byte address. 3. d 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates the last two bus cycles of a four bus cycle sequence. addresses fwe oe fcs data 5.0 v 5555h pa pa t wc t ws pd d 7 d out t ah t cph t cp t dh t ds data polling t as t ghel a0h t whwh1 wsf512k16-xxx
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com package 402: 66 pin, pga type, ceramic hex-in-line package, hip (h2) 35.2 (1.385) 0.38 (0.015) sq 25.4 (1.0) typ 15.24 (0.600) typ 0.76 (0.030) 0.1 (0.005) 5.7 (0.223) max 3.81 (0.150) 0.1 (0.005) 2.54 (0.100) typ 25.4 (1.0) typ 1.27 (0.050) 0.1 (0.005) 1.27 (0.050) typ dia 0.46 (0.018) 0.05 (0.002) dia pin 1 identifier square pad on bottom all linear dimensions are millimeters and parenthetically in inches wsf512k16-xxx
14 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com package 500: 68 lead, ceramic quad flat pack, cqfp (g2) 0.38 (0.015) 0.05 (0.002) 0.25 (0.010) 0.1 (0.002) 25.1 (0.990) 0.25 (0.010) sq 1.27 (0.050) typ 24.0 (0.946) 0.25 (0.010) 22.4 (0.880) 0.25 (0.010) sq 20.3 (0.800) ref 5.1 (0.200) max 0.25 (0.010) 0.127 (0.005) 23.87 (0.940) ref 1.0 (0.040) 0.127 (0.005) 0.25 (0.010) ref 1 / 7 r 0.25 (0.010) detail a see detail "a" pin 1 all linear dimensions are millimeters and parenthetically in inches 0.940" typ the wedc 68 lead g2 cqfp fills the same fit and function as the jedec 68 lead cqfj or 68 plcc. but the g2 has the tce and lead inspection advantage of the cqfp form. wsf512k16-xxx
15 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com lead finish: blank = gold plated leads a = solder dip leads device grade: m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c package type: h2 = ceramic hex in-line package, hip (package 402) g2 = 22 mm ceramic quad flat pack, cqfp (package 500) access time (ns) 39 = 35ns sram and 90ns flash 72 = 70ns sram and 120ns flash also available organization, 512k x 16 flash sram white electronic designs corp. ordering information w s f 512k16 - xxx x x x device type sram speed flash speed package smd no. 512k x 16 mixed module 70ns 120ns 66 pin hip (h2) 5962-96901 01hxx 512k x 16 mixed module 35ns 90ns 66 pin hip (h2) 5962-96901 02hxx 512k x 16 mixed module 70ns 120ns 68 lead cqfp/j (g2) 5962-96901 01hmx 512k x 16 mixed module 35ns 90ns 68 lead cqfp/j (g2) 5962-96901 02hmx wsf512k16-xxx

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